Taiwan Semiconductor Manufacturing Co.’s decision to delay adopting ASML Holding NV’s most advanced chipmaking equipment sent conflicting shockwaves through the semiconductor market, boosting its own stock by 5% while wiping out nearly $17 billion of ASML’s market value. The move casts uncertainty on the adoption timeline for the industry’s next frontier in miniaturization, even as analysts view the delay as a matter of timing rather than a structural shift in demand.
“We continue to be able to harvest the benefit from current EUV,” Kevin Zhang, TSMC’s deputy co-chief operating officer, told reporters, calling the next-generation high-NA EUV machines “very, very expensive.” The machines from the Dutch equipment maker are priced at over €350 million ($400 million), roughly double the cost of previous models, a price TSMC has deemed prohibitive for mass production through 2029.
The market reaction was immediate and divergent. ASML’s U.S.-traded shares fell as much as 5.5% after the announcement from its single largest customer. In contrast, TSMC’s stock jumped 5% as investors showed confidence in its strategy to enhance performance and efficiency without the costly upgrade. The company revealed it would leverage its new, more economical A13 and N2U manufacturing nodes, set for 2029 and 2028 respectively, alongside advanced packaging solutions.
This strategic pivot by the world’s largest foundry creates a potential opening for its chief rivals, Intel Corp. and Samsung Electronics Co. Both have expressed more positive views on acquiring the high-NA EUV technology, which could allow them to close the technology gap with TSMC. “While TSMC may adopt High-NA later than we initially expected, this opens the door for other foundry and logic customers to move earlier and differentiate,” UBS analysts wrote in a client note.
At the heart of TSMC’s decision is a complex cost-benefit analysis. The company plans to continue using its current generation of extreme ultraviolet (EUV) lithography tools while pushing the boundaries of chip design through other means. At its recent Santa Clara technology symposium, TSMC detailed plans for multi-chip stacking that would allow it to package 10 large computing chips with 20 high-bandwidth memory stacks by 2028. This is a significant leap from today’s technology, seen in processors like Nvidia’s Vera Rubin which integrates two large chips and eight memory stacks. This focus on advanced packaging represents an alternative path to boosting performance as transistor miniaturization slows.
While TSMC projects confidence, its delay is not without risk. Should competitors like Intel or Samsung successfully integrate high-NA EUV into their high-volume manufacturing sooner, they could potentially offer superior performance or efficiency, challenging TSMC’s market dominance. For now, however, analysts at firms like Citigroup are framing the move as consistent with TSMC’s historically cautious approach to capital expenditure. They noted that significant orders for the high-NA machines were not expected before 2028 anyway, suggesting the market’s initial reaction may have been overblown. The decision underscores the immense and growing cost of staying at the bleeding edge of semiconductor manufacturing, forcing even the industry leader to weigh the price of progress.
This article is for informational purposes only and does not constitute investment advice.
