IBM unveils sub-1nm chip with 50% performance gain over 2nm node

IBM's nanostack architecture packs nearly 100 billion transistors onto a fingernail-sized chip, extending Moore's Law into the angstrom era.

IBM unveiled the semiconductor industry's first sub-1-nanometer chip technology, a vertically stacked transistor architecture that packs nearly 100 billion transistors onto a fingernail-sized die — nearly double the density of its 2nm node.

"It's not just an incremental step, it's a meaningful leap forward, pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy," Jay Gambetta, director of IBM Research and an IBM Fellow, said.

The 0.7-nanometer, or 7-angstrom, node delivers up to 50 percent higher performance or 70 percent greater energy efficiency compared with IBM's 2nm node chips introduced in 2021, according to published technical results. The nanostack architecture builds on nanosheet technology — which IBM pioneered and which has become the industry standard for 3nm and 2nm chips at TSMC and other foundries — by stacking transistors vertically rather than shrinking features across the wafer surface.

The breakthrough extends the semiconductor roadmap for at least another decade, threatening to widen the technology gap for competitors still scaling nanosheet transistors in two dimensions. IBM expects commercial adoption within five years and mainstream production within a decade, potentially reshaping the competitive dynamics among TSMC, Samsung Foundry and Intel.

The nanostack design uses sequential 3D integration to bond two transistors — each containing three nanosheets 5 nanometers thick, equivalent to about 15 rows of silicon atoms — into a single stacked unit. The architecture allows top and bottom transistors to be engineered separately with different materials, enabling performance and power optimizations that are difficult in conventional planar structures.

IBM researchers demonstrated the technology's viability through functional CMOS inverter operation with expected switching performance, presented at the 2025 IEEE Symposium on VLSI Technology and Circuits. At the VLSI 2026 symposium, the company showed a 40 percent improvement in SRAM scaling using a staggered-channel design that reduces bit-cell height — a development Gambetta said could prove significant for AI workloads requiring high-bandwidth, high-efficiency memory close to compute resources.

The SRAM scaling achievement addresses a growing bottleneck in AI chip design. SRAM scaling improved only a few percent between the 3nm and 2nm generations, Gambetta said, making the 40 percent gain a structural shift for chip architects designing AI accelerators that rely heavily on on-chip memory to reduce data movement — one of the largest sources of energy consumption in AI inference.

Huiming Bu, vice president of silicon technology research and development at IBM, said the industry has largely scaled transistors in two dimensions since the metal-oxide-semiconductor field-effect transistor was invented in 1959. "This will be for the first time in our industry that we are able to stack and stagger transistors in a vertical direction," he said.

The work is being conducted at IBM's semiconductor research facility in Albany, New York, where the company and its partners — including Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions — are preparing to deploy High Numerical Aperture Extreme Ultraviolet lithography from ASML Holding NV. IBM said High NA EUV will be critical for future logic scaling and could also improve nanosheet technology before nanostack reaches production.

IBM has not disclosed commercialization partners for nanostack, though it is working with Japan's Rapidus Corp. on 2nm manufacturing. The company's track record of licensing its chip technology to partners including Samsung suggests a similar model for nanostack. TSMC, which independently developed nanosheet transistors for its 2nm node after IBM's pioneering work, faces pressure to develop its own 3D stacking solution to remain competitive.

For investors, the implications span multiple tickers. IBM's breakthrough could pressure TSMC and Intel to accelerate their own sub-1nm roadmaps, potentially increasing R&D spending across the industry. If nanostack delivers the projected 50 percent performance gain, it could shift procurement decisions at hyperscale cloud operators — Amazon, Microsoft and Google — that spend tens of billions annually on AI chips. IBM itself, while not a commercial chip manufacturer, stands to generate licensing revenue from the architecture, though the company has not disclosed financial terms.

This article is for informational purposes only and does not constitute investment advice.