Cadence and TSMC deepen partnership to accelerate AI chips with 2nm technology

Cadence and TSMC are expanding their collaboration to give chip designers early access to next-generation manufacturing processes, aiming to cut down the time it takes to develop more powerful and efficient AI hardware.

Cadence Design Systems Inc. (Nasdaq: CDNS) is expanding its long-standing relationship with Taiwan Semiconductor Manufacturing Co. (TSMC) to accelerate the development of artificial intelligence-driven silicon. The collaboration will provide chip designers with early access to certified tools and intellectual property (IP) for TSMC’s most advanced process nodes, including the upcoming A14 and N2 technologies, aiming to reduce design iterations and speed time to market for complex AI and high-performance computing (HPC) chips.

"The growing demands of AI compute workloads, combined with compressed design cycles, require advanced, energy-efficient silicon technologies, streamlined design flows, and silicon-validated IPs," said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. "Through our collaboration with Open Innovation Platform® (OIP) ecosystem partners like Cadence, we empower customers to confidently design cutting-edge silicon using TSMC's latest process technologies."

The partnership gives customers access to a comprehensive suite of Cadence’s digital and custom/analog tools, which have been certified for TSMC’s N2 and A16 nodes. This includes Cadence’s flagship EDA platforms like the Innovus Implementation System and Virtuoso Studio. The collaboration also extends to advanced packaging, with the Cadence Integrity 3D-IC Platform supporting TSMC’s latest 3DFabric technologies, which are critical for building the large, complex systems required for generative AI.

This deeper integration between the two companies is critical for an industry grappling with the immense costs and complexity of designing at the frontier of Moore's Law. For companies like Nvidia, Arm, and emerging AI accelerator startups, having validated and optimized tools and IP for TSMC’s newest manufacturing processes can shave months off development cycles and reduce the risk of costly chip failures, a crucial advantage in the fast-moving AI hardware market.

Next-Generation Nodes and Agentic AI

A key focus of the collaboration is TSMC’s next wave of process technology, including the A14 and N2 nodes. TSMC's A14 is a direct shrink of its A16 technology, offering a 6% area saving with full design rule compatibility, allowing for a smoother transition for customers. The N2 process, TSMC’s first to use nanosheet transistors, is also getting an update with N2U, which offers further performance gains and power reduction.

Cadence is preparing its software for these future nodes by developing what it calls "agent-ready" design flows. This involves integrating agentic AI into its EDA tools, a strategy the company calls "Design for AI and AI for Design." The goal is to shift from engineers manually running tools to an AI agent orchestrating the entire chip design process, from initial concept to final signoff.

"AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures," said Chin-Chi Teng, senior vice president and general manager at Cadence. "Through collaboration with TSMC, we're advancing our Design for AI and AI for Design strategy by uniting certified flows with silicon-proven IP."

Customer Momentum and Competitive Landscape

The partnership is already seeing traction with customers. The press release highlights early and mainstream companies actively designing on TSMC's 3nm and 2nm technologies. Positron, an AI inference accelerator startup, is using Cadence's PCIe 6.0 IP on TSMC's N3P process. This underscores the importance of having pre-verified, high-speed interface IP, which is a significant bottleneck in chip design.

The collaboration positions Cadence and TSMC to maintain their leadership in the face of growing competition. While TSMC is the dominant foundry for advanced AI chips, it faces challenges from Samsung Foundry and a resurgent Intel Foundry Services. By working closely with key ecosystem partners like Cadence, TSMC creates a stickier platform for chip designers, making it harder for competitors to gain a foothold. For Cadence, the tight integration with TSMC’s roadmap ensures its tools remain indispensable for companies building the most advanced chips, a market worth billions of dollars annually.

This article is for informational purposes only and does not constitute investment advice.