AMD to invest over $10 billion in Taiwan to scale AI chip packaging

(P1) Advanced Micro Devices is investing more than $10 billion across Taiwan's semiconductor ecosystem to secure a critical supply chain for its next-generation AI hardware, a direct move to address the advanced packaging bottleneck ahead of major product launches. The investment, announced May 21, aims to scale manufacturing of high-bandwidth, power-efficient interconnects essential for future AI data centers.

(P2) "As AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand,” said Dr. Lisa Su, Chair and CEO of AMD. “By combining AMD leadership in high-performance computing with the Taiwan ecosystem and our strategic global partners, we are enabling integrated, rack-scale AI infrastructure that helps customers accelerate deployment of next-generation AI systems.”

(P3) The investment deepens collaboration with key Taiwanese packaging firms, including ASE Technology Holding and Siliconware Precision Industries (SPIL), to develop and qualify next-generation wafer-based 2.5D bridge interconnects. This technology, called Elevated Fanout Bridge (EFB), is designed to boost interconnect bandwidth and power efficiency for AMD’s upcoming 6th Gen EPYC CPUs, codenamed “Venice.”

(P4) This entire effort is designed to ensure the on-time deployment of the AMD Helios rack-scale platform in the second half of 2026. The platform, which features AMD’s Instinct MI450X GPUs and “Venice” CPUs, is aimed at multi-gigawatt AI deployments, making the success of these packaging partnerships critical to AMD’s ability to capture a larger share of the AI infrastructure market.

EFB Packaging Aims for Higher Bandwidth

AMD’s strategy centers on solving a key physical limitation in AI systems: how to move massive amounts of data between chips quickly and efficiently. The company is focusing on Elevated Fanout Bridge (EFB) architecture, a 2.5D packaging technology that increases interconnect density and improves power efficiency. This allows for faster, more efficient systems that deliver greater performance-per-watt.

The collaboration with ASE and SPIL focuses on industrializing this wafer-based EFB technology. "Our collaboration with AMD on Elevated Fanout Bridge technology represents a significant step forward in scaling advanced packaging for high-volume applications,” said Steven Tsai, Senior Vice President of Sales at ASE. In a parallel effort, AMD announced it has qualified the industry’s first 2.5D panel-based EFB interconnect with partner PTI, a milestone that supports high-bandwidth interconnect at a larger scale and improved cost.

Helios Platform and Ecosystem on Track for 2026

The packaging advancements are not happening in a vacuum; they are foundational to AMD’s ambitious AMD Helios rack-scale system. Leading original design manufacturers (ODMs) including Sanmina, Wiwynn, Wistron, and Inventec are building out Helios-based systems. These platforms will integrate AMD’s flagship AI chips—the Instinct MI450X GPU and the 6th Gen EPYC CPU—with its ROCm open software stack.

The goal is to deliver a fully integrated system that allows customers to run larger, more complex AI workloads while optimizing for power and efficiency. The public backing from a wide range of supply chain partners, from packagers like ASE and SPIL to substrate suppliers like Unimicron and Nan Ya PCB, signals a coordinated effort to prepare for high-volume manufacturing ahead of the 2H 2026 launch window. The investment de-risks the production ramp, a crucial step as AMD competes with Nvidia's own aggressive hardware roadmap. Failure to meet the 2026 timeline or qualify the EFB technology at scale would represent a significant risk to AMD's revenue and market share ambitions in the AI space.

This article is for informational purposes only and does not constitute investment advice.