Synopsys Partners With Lightmatter on 3nm Optical Tech for AI Infrastructure

Edgen Stock

·Jan 27 2026, 20:29

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Key Takeaways

Lightmatter and Synopsys announced a strategic collaboration to integrate advanced interface technology into a photonic computing platform, aiming to resolve critical bottlenecks in AI data centers. The partnership leverages Synopsys's expertise in high-speed connectivity with Lightmatter's leadership in co-packaged optics.

Synopsys will provide its 224G SerDes and UCIe IP for integration into Lightmatter's Passage™ platform.
The joint effort focuses on developing a low-latency Co-Packaged Optics (CPO) solution on an advanced 3nm process node.
This collaboration directly targets performance limitations in next-generation AI hardware, addressing data movement and power consumption issues.

Synopsys Integrates 224G IP into Lightmatter's 3nm Optical Platform

On January 26, 2026, Synopsys and photonic computing leader Lightmatter announced a strategic collaboration to accelerate the development of next-generation AI hardware. The partnership involves integrating Synopsys's advanced 224G SerDes and Universal Chiplet Interconnect Express (UCIe) IP, designed for a 3nm process, into Lightmatter's Passage™ 3D Co-Packaged Optics (CPO) platform. This move combines Synopsys's industry-leading silicon interface technology with Lightmatter's specialized photonic interconnect solutions.

Partnership Targets AI Data and Power Bottlenecks

The collaboration is designed to directly address two of the most significant challenges in scaling AI systems: data latency and power consumption. As AI models grow in complexity, the electrical interconnects used in traditional data centers become a major bottleneck, limiting performance and driving up energy costs. By developing a robust, low-latency CPO platform, the companies aim to bring optical connectivity closer to the compute silicon, enabling faster and more efficient data transfer between chips. This integration is critical for building the high-performance, scalable infrastructure required for future AI and high-performance computing (HPC) workloads, potentially giving both firms a key advantage in the competitive AI hardware market.