SK Hynix Targets HBM4 Leadership by Solving 2048 I/O Bottleneck
SK Hynix is developing a new packaging architecture for its next-generation HBM4 memory, aiming to meet the demanding performance specifications set by NVIDIA. The primary challenge stems from HBM4's design, which doubles the input/output (I/O) count to 2048 compared to its predecessor. This density dramatically increases the risk of signal interference and complicates power delivery from the bottom logic chip to the top DRAM layers, necessitating a fundamental redesign of the packaging structure.
Novel Packaging Boosts Performance Without Major Capital Outlay
SK Hynix's solution, currently in the validation phase, involves two key structural changes. First, it increases the thickness of the DRAM chips, contrary to the conventional thinning process. This enhances the stack's physical stability and reduces yield loss from external stress, a critical factor for maintaining performance within HBM4's 775-micron total height requirement. Second, to compensate for the thicker chips, the technology shrinks the distance between DRAM layers. This closer proximity improves data transfer speeds and lowers the power needed to operate the memory stack.
The most significant commercial advantage of this approach is its potential to boost performance without requiring massive capital expenditures on new equipment or process flows. If SK Hynix can successfully scale this technology, it could solidify its lead over rivals Samsung and Micron. However, the company still faces the challenge of mass production. Specifically, the narrower layer spacing makes it difficult to inject the protective Molded Underfill (MUF) material evenly, a critical step to prevent defects. Overcoming this hurdle will determine the timeline for commercialization.
Edgen Stock·Mar 03 2026, 12:45
