Siemens is turning its chip design AI agents into self-verifying systems that check every decision against physics-based engines, targeting 10x faster characterization and a 5x to 10x reduction in token costs.
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Siemens and Nvidia target 10x speedup with self-verifying chip AI
Siemens is turning its chip design AI agents into self-verifying systems that check every decision against physics-based engines, targeting 10x faster characterization and a 5x to 10x reduction in token costs.
Siemens is closing the loop on AI agents in chip design by forcing them to validate every decision against deterministic signoff tools, targeting 10x faster library characterization and 5x to 10x lower token costs. The expanded partnership with Nvidia, announced July 26, turns the Fuse EDA AI Agent system into what Siemens calls a self-verifying workflow — long-running agents that check their own work against the same engines that decide whether a design passes.
"Our expanded collaboration with NVIDIA enhances our domain-specific industrial AI, physics-based EDA engines and accelerated computing to create trusted, self-verifying AI workflows," said Amit Gupta, senior vice president and chief AI strategy officer at Siemens EDA.
The Fuse EDA AI Agent system, first introduced in March 2026 at Nvidia's GTC conference, now integrates with Siemens' Intelligence Center X enterprise AI environment. It runs on Nvidia's NeMo Gym library for agentic training, the OpenShell secure runtime with role-based access controls and audit trails, and Nemotron models with Switchyard for reasoning. The agents span the full design flow — from Catapult high-level synthesis and Questa One verification through Solido custom IC design, Aprisa physical implementation, Calibre signoff and Tessent design-for-test, plus 3D IC integration in Innovator3D IC and board layout in Xpedition.
The announcement comes as Siemens, Synopsys and Cadence compete to sell agentic AI to chip teams that have been slow to trust language models with silicon. Verification alone consumes as much as 70 percent of design effort, according to Siemens. Nvidia shares, trading at roughly 35x forward earnings, stand to benefit as its AI infrastructure becomes embedded in industrial EDA workflows — a market IDC estimates at $14 billion annually.
The Trust Problem in Agentic Chip Design
The core innovation is architectural: instead of letting an AI model's output stand on its own, Siemens routes each agent decision through its deterministic signoff engines — Calibre for design-rule checking, Questa One for functional verification — which return pass-or-fail answers independent of the model's judgment. This addresses the fundamental reason chip teams have been cautious about handing real work to large language models: a confident error in register-transfer level code or a missed design-rule violation surfaces only at tapeout, after mask costs are sunk.
"The ability to relate layout insight directly to electrical behavior is critical," said Gianbattista Lo Giudice, non-volatile memory design manager at STMicroelectronics, the one named customer in the release. His team is "planning to test and validate the advantages in our on-going design activity."
Two Products, One Unverified Speed Claim
The concrete deliverables are the Solido Characterization Suite with agentic workflows that generate and verify Liberty timing files, and the new Solido Layout Analyzer, which applies natural-language prompting to parasitic and layout-dependent effects in post-layout designs. Siemens claims the characterization workflow cuts turnaround times by more than 10x and reduces token costs by 5x to 10x. Nvidia's own announcement of the same collaboration puts the token-cost reduction at more than 10x — a discrepancy neither company has explained. Neither release names the design, process node, or engineer-hours used as the baseline.
On the verification side, Siemens is pairing its Questa One Agentic Toolkit, introduced in February 2026, with Nvidia's Nemotron 3 Ultra reasoning model. Siemens says the model leads among open models in agentic RTL benchmarking, citing ACE-RTL — an agent built by Nvidia Research, measured on a Verilog problem set Nvidia itself publishes.
Investment Angle
The agentic layer is where the three big EDA vendors — Siemens, Synopsys and Cadence — are competing on speedups that no independent body has audited. What is verifiable is Siemens' acquisition activity: in the week before the Design Automation Conference, it bought Precision Innovations, a San Diego firm building AI-driven chip planning on the open-source OpenROAD framework, and Defacto Technologies, a Grenoble developer of automated system-on-chip assembly. Terms were not disclosed for either. Those purchases give the Fuse agent system more design-creation and planning tools to call — a tangible commitment that matters more than the unverifiable 10x claims.
This article is for informational purposes only and does not constitute investment advice.
[1] Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design[2] Silvaco to Accelerate Physics-Based Digital Twins for Semiconductor Design and Manufacturing Using NVIDIA AI and Accelerated Computing[3] Siemens Makes Its Chip Design AI Agents Check Their Own Work[4] Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology
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